1. Field of the Invention
The invention relates to a fast Fourier transform (FFT) processor, and more particularly to a FFT processor capable of operating both a radix-2.sup.n algorithm and a radix-2.sup.(n+1) algorithm.
2. Description of the Related Art
In the wireless field, various modulation and demodulation methods are widely investigated for increasing the sensitivity and accuracy of the received radio frequency (RF) signal, wherein the orthogonal frequency division multiplexing (OFDM) shows the most potential. In OFDM, the modulation and the demodulation are respectively completed by IFFT (Inverse Fast Fourier Transform) and FFT, however, one FFT processor or IFFT processor can only operate one Fourier algorithm, for example, an FFT processor of an OFDM modulator for the UWB specification processes only one hundred and twenty eight point data.
When implementing FFT, many architecture types are used, such as radix-2, radix-4, radix-8, radix-22, radix-23 and so on, wherein radix-22, radix-23 architectures are widely applied in integrated circuits due to decreasing the number of complex number multipliers. A complex number multiplier is implemented by one adder and two multipliers in circuit design, and if the complex number multipliers decrease, the layout area of the FFT processor decreases.
The architecture of radix-22 can process the data with all 4n point data, such as 1, 4, 16, 64 point data and so on, and the architecture of radix radix-23 can process the data with all 8n point data, such as 1, 8, 64, 512 point data and so on. However, if the data is neither 4n point data nor 8n point data, such as 128 or 2048 point data, the architecture of radix-2 may be applied, thus, the number of complex number multipliers increases and the layout area of the FFT circuit increases.
Furthermore, the conventional OFDM processor is suited for only one wireless specification, and if a RF receiver is designed to process different wireless specification data, different OFDM processors are required, thus, the cost and the layout area of the receiver increase.